:Design and simulate a single-ended two-stage OTA with PMOS input differential pair and NMOS second stage to meet the following specifications VDD=1.8V Load Capacitance: 3 pF DC Gain > 1000 fta> 300 MHz PM > 65o for B=1 Input CM range: At least 0.5 V to 0.9V Output swing (peak-to-peak)> 1.4Vpp Power dissipation: As low as possible Estimate required MOS parameters by simulating single NMOS and PMOS transistors. Use basic equations and your knowledge to have a staring design point (W/L and current of transistors, CC and RZ). describe your design flow. Implement your design in the 0.18um technology in the TT-27oC corner case. If the results are far from the required specifications, optimize the circuit. describe your optimization flow For the designed OTA, simulate the frequency response (phase and magnitude) and show DC gain, PM, and fT. Prove that your OTA works in the input CM and output swing range by proper simulations. Chage corners to SS 120 and FF -40. Repeat part 4 again. Modify your circuit if necessary to make sure tour design meet the specs.
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